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Note: Links lead to the DBLP on the Web. P. Pal Chaudhuri Sukanta Das , Biplab K. Sikdar , P. Pal Chaudhuri: Characterization of Reachable/Nonreachable Cellular Automata States. ACRI 2004 : 813-822 Partha Sarathi Bhattacharjee , Sajal K. Das , Debashis Saha , D. Roychowdhury , P. Pal Chaudhuri: A Parallel Architecture for Video Compression. VLSI Design 1997 : 247-252 S. Bhattacharjee , J. Bhattacharya , U. Raghavendra , D. Saha , P. Pal Chaudhuri: A VLSI architecture for cellular automata based parallel data compression. VLSI Design 1996 : 270-275 S. Mitra , S. Das , P. Pal Chaudhuri, S. Nandi : Architecture of a VLSI Chip for Modeling Amino Acid Sequence in Proteins. VLSI Design 1996 : 316-317 S. Nandi , P. Pal Chaudhuri: Theory and applications of cellular automata for synthesis of easily testable combinational logic. Asian Test Symposium 1995 : 146-152 Vishwani D. Agrawal , Bernard Courtois , Fumiyasu Hirose , Sandip Kundu , Chung-Len Lee , Yinghua Min , P. Pal Chaudhuri: Panel: New Research Problems in the Emerging Test Technology. Asian Test Symposium 1995 : 189- S. Chattopadhyay , S. Roy , P. Pal Chaudhuri: Technology mapping on a multi-output logic module built around Cellular Automata Array for a new FPGA architecture. VLSI Design 1995 : 57-62 Sudipta Bhawmik , P. Pal Chaudhuri: DFTEXPERT: An Expert System for Design of Testable VLSI Circuits. IEA/AIE (Vol. 1) 1988 : 388-396 J. S. R. Subrahmanyam , P. Pal Chaudhuri: A Divide and Conquer Testing Strategy for Detection of Multiple Faults by SFDTS. ITC 1986 : 997-1006 1 [ 4 ] 2 [ 8 ] 3 [ 7 ] 4 [ 7 ] 5 [ 2 ] 6 [ 3 ] 7 [ 4 ] 8 [ 6 ] 9 [ 8 ] 10 [ 9 ] 11 [ 4 ] 12 [ 4 ] 13 [ 4 ] 14 [ 4 ] 15 [ 6 ] 16 [ 5 ] [ 6 ] 17 [ 7 ] 18 [ 3 ] 19 [ 8 ] 20 [ 7 ] 21 [ 8 ] 22 [ 9 ] 23 [ 1 ]  ©2005 Association for Computing Machinery |
